1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming FinFET devices with alternative channel materials.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region, and a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B. The device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. The gate structure D is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions.
In the FinFET device A, the gate structure D encloses both sides and the upper surface of all or a portion of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as so-called III-V materials, to manufacture FinFET devices, which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation.
However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is a non-trivial matter due to, among other issues, the large difference in lattice constants between such alternative materials and silicon. That is, in the case where an alternative fin material (not shown in FIG. 1A) is formed on a fin C defined in the substrate B, i.e., a substrate fin C, the lattice constant of the alternative fin material may be greater than the lattice constant of the substrate fin C. As a result of this mismatch in lattice constants, an unacceptable number of defects may be formed or created in the alternative fin material portion.
One process that has been investigated for use in forming such alternative fin materials is known as aspect-ratio-trapping (ART). In general, the ART process involves forming a masking layer, such as silicon dioxide, above a semiconductor substrate, such as silicon, patterning the masking layer to define a trench that exposes the underlying substrate, and performing an epitaxial growth process to form an alternative fin material, e.g., silicon/germanium, on the exposed substrate, wherein the growth is confined within the trench. That is, the ART process involves epitaxially growing fully relaxed, unstrained material hetero-structures in a high aspect-ratio silicon dioxide trench having an aspect ratio of 5 or greater in an effort to decrease defects. In some applications, the ART process may involve the formation of trenches that have a very high aspect ratio, e.g., about 25-30. Importantly, in the ART process, the trench is made deep enough such that defects generated in the alternative fin material will be trapped at or near the bottom of the original trench and in the sidewalls of the trench positioned slightly above the interface between the substrate material and the alternative fin material. The amount of defects generated and the propagation of such defects will depend upon the crystal orientation of the substrate. The intent of the ART process is that, while the defect-containing fin material is present at or near the bottom of the trench, the uppermost portions of the epitaxially grown alternative fin material will be substantially defect-free material but, importantly, it is an unstrained material. That is, the alternative fin material is fully relaxed in all crystalline planes, e.g., in the crystalline planes that correspond to the axial length direction, height direction and width direction of the fin. This occurs due to the “trapping” of the defects at or near the bottom of the trench, with the result being the formation of substantially defect-free alternative fin material above the defective-containing portions of the alternative fin material in the lower portion of the trench. The ART process reduces the thickness of the material requirement for non-defective growth in comparison to the blanket growth of a similar structure. However, in the ART growth process, there are intentionally-formed defects present in the bottom portion of the alternative fin material as well as defects at the interface of the hetero-structure, and the grown material is typically relatively thick, e.g., about 200-300 nm, which corresponds to the fin height direction. The defects are generated along the <111> crystallographic direction of the alternative fin material and they are captured or stopped by the sidewalls of the trench.
Another prior art process that has been employed to form alternative fin materials on silicon substrate fins is simplistically depicted in FIGS. 1B-1E. FIG. 1B depicts the prior art device 10 after several process operations were performed. First, an etching process, such as a dry or wet etching process, was performed on the substrate 12 through a patterned hard mask layer (not shown) to form a plurality of trenches 14 in the substrate 12. This etching process results in the definition of a plurality of substrate fins 16. Then, as shown in FIG. 1C, a layer 18 of alternative semiconductor material, e.g., silicon/germanium, is formed on the substrate fins 16 and within the trenches 14 by performing an epitaxial deposition process. Then, as shown in FIG. 1D, a layer of insulating material 22, e.g., silicon dioxide, is formed in the trenches 14 of the device such that it overfills the trenches 14. Next, as shown in FIG. 1E, an etching process, such as a dry, wet or vapor phase etching process, was performed to reduce the thickness of the layer of insulating material 22, a process that essentially defines the final fin height of the fins. At the point depicted in FIG. 1E, a gate structure, either a permanent gate structure or a sacrificial gate structure (neither of which is shown) would be formed on the fins using traditional techniques.
Another prior art process that has been employed to form alternative fin materials on silicon substrate fins is simplistically depicted in FIGS. 2A-2D. FIG. 2A depicts the prior art device 10 after several process operations were performed. First, an etching process, such as a dry or wet etching process, was performed on the substrate 12 through a patterned hard mask layer (not shown) to form a plurality of trenches 14 in the substrate 12. As before, this etching process results in the definition of a plurality of substrate fins 16. Then, as shown in FIG. 2B, the above-described layer of insulating material 22, e.g., silicon dioxide, was formed in the trenches 14 of the device such that it overfills the trenches 14. Next, as shown in FIG. 2C, an etching process, such as a dry, wet or vapor phase etching process, was performed to reduce the thickness of the layer of insulating material 22, a process that essentially defines the final fin height of the fins. Then, as shown in FIG. 2D, the above-described layer 18 of alternative semiconductor material, e.g., silicon/germanium, was formed on the exposed portions of the substrate fins 16 by performing an epitaxial deposition process. At the point depicted in FIG. 2D, a gate structure, either a permanent gate structure or a sacrificial gate structure (neither of which is shown) would be formed on the fins using traditional techniques.
The present disclosure is directed to methods of forming FinFET devices with alternative channel materials that may solve or reduce one or more of the problems identified above.